Reducing the level of spurious components in the phase-locked loop frequency synthesizer

Abstract

This work is concerned with reducing the level of spurious components in the synthesizer phase-locked loop fractional-n frequency divider in feedback circuit. It is noted one of the drawbacks of such a scheme is the interference generated by the synthesizer, since it has a parasitic relationship between the synthesized signal and the input frequency-phase detector from the reference source. It is shown that the output side (parasitic) spectral components due to the fact that the synthesized frequency is not a multiple of the frequency of the input signal detector (not a multiple of the frequency comparison). It is noted that the worst case occurs when the difference between the synthesized frequency and the nearest frequency is a multiple of the frequency of comparison, is so small that the lowpass filter of the auto-tuning system does not provide the required suppression of spurious components. The proposed scheme improved synthesizer with reduced spurious performance. Shown the main advantage of the proposed scheme is that by introducing new nodes is the ability to reduce the spurious in the output signal taking into account the impact of switching reference oscillator for the duration of the transients. Recommendations on the use of the proposed synthesizer are promising systems that require low spurious components in the output signal with small overall dimensions and power consumption of the device.