Stimulus generator for SEIR method based ADC BIST

Abstract

Testing of ADC in SOC is a significant challenge since it usually has no connection to the outside. Built-in self-test (BIST) is regarded as a promising alternative to traditional test. Most reported ADC BIST research works try to replicate a production test scheme on chip. This approach requires input ramp with high linearity which is hard to achieve on chip. This paper investigates signal generator implementation issues of adapting stimulus error identification and removal method which was presented for production test into a practical ADC BIST solution. A stimulus generator using very small transistor count is presented. Extremely simple methods for generating small constant voltage level shifts are introduced and evaluated. Simulation results show that generated signals with less than 7 bits linearity, together with the simple level shifts, are able to test a 16-bit ADC to 16 bit accuracy level. These results demonstrate that accurate BIST of deeply embedded AMS blocks may be practically implemented on chip with very low overhead.