A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA

Abstract

Polynomial evaluation is currently used in multiple domains such as image processing, control systems and applied mathematics. Its high demand in calculation time and the need for embedded solutions make it a good target application for a hardware-oriented solution. This paper presents a new scalable architecture and its FPGA implementation designed to exploit the high level of parallelism present in such applications. Illustrated by an example in the field of 3-D graphic computation, results show important acceleration factors varying from 178 to 880 for orders ranging from 4 to 19, while the associated hardware cost scales linearly with polynomial order. Moreover using parallel implementations of the architecture to evaluate multiple polynomials, acceleration factor as high as 30858 can be obtained compared to an execution on a single processor.