Robert T. Nericua, George Vinfred S. Maraat, Re-Ann Cristine O. Calimpusan, O. J. Gerasta, J. Hora
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引用次数: 0
Abstract
This study presents a design of low power 3rd order 16-bit Sigma Delta Analog to Digital Converter in Feedforward Architecture with Integrator Time Multiplexing Technique implemented in TSMC 65nm CMOS technology. The designed is composed of a 3rd-order modulator in feedforward architecture to improve loop stability and with integrator time multiplexing technique for reduction of power consumption. The Analog to Digital Converter (ADC) is designed to consume a total power of 0.342mW and with a modulator sampling rate of 25600Hz. This ADC uses a 2V supply for analog circuit blocks and a 1V supply for digital circuit block. The ADC has a dimension of 333.35um x 241.64um.
本研究提出一种采用积分器时间复用技术的低功耗三阶16位Sigma Delta前馈模数转换器的设计方案。该系统采用前馈三阶调制器结构，提高了系统的稳定性，同时采用积分器时间复用技术，降低了系统功耗。模数转换器(ADC)的设计功耗为0.342mW，调制器采样率为25600Hz。该ADC采用2V模拟电路模块和1V数字电路模块。ADC的尺寸为333.35um x 241.64um。
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