Low noise amplifier at 4GHz frequency for DBS application

Abstract

This paper presents the design and simulation of a narrow band Low Noise Amplifier (LNA) based on 180nm CMOS technology. This LNA consists of 2-stage design in which common source stage is followed by cascade stage. Different matching techniques is used at input, output and intermediate stage in the design to obtain the best result and to minimize the loss as much as possible. The LNA is designed for low power, high gain applications and it provides a series of good performance like noise figure, linearity, figure of merit (FOM) and power consumption. The proposed LNA is design and simulated using Agilent Advance design system in an 180nm CMOS technology and measurement results shows voltage gain of 38dB noise figure of 1.867 dB at 4 GHz frequency which is best suited for DBS application.