Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits

2011 14th Euromicro Conference on Digital System Design Pub Date : 2011-08-31 DOI:10.1109/DSD.2011.92

M. Bryk, L. Józwiak, W. Kuzmicz

引用次数: 1

Abstract

This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days.

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纳米cmos电路泄漏功率的快速准确估计

本文讨论了在纳米cmos技术中实现的电路的静态功耗降低的关键问题。其解决方案要求准确、快速的功率估计，但目前已知的功率模拟器并不能同时做到准确和快速。本文提出并讨论了一种新的快速、高精度的泄漏功率估计方法及其仿真器。模拟器的最大估计误差在5%以内，平均误差仅为0.57%，运行时间在秒范围内，而对于相同的电路，HSPICE的运行时间为数小时或数天。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2011 14th Euromicro Conference on Digital System Design

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