A 100Ms/s 12-bit 1.8V low power switched capacitor class A/B sample-and-hold amplifier

Abstract

The sample and hold amplifier plays an important role in the front end of an analog to digital converter. In this work, a low power, high resolution, and high speed sample and hold amplifier is presented. The architecture of the proposed mainly adapts the class A/B folded cascode amplifier with a gain boosting technique and a switch capacitor common mode feedback scheme. The performance comparisons among different designs show that the proposed work achieves the lowest power consumption. The operation speed of the proposed design is 100Ms/s for a 12-bit resolution ADC by using the TSMC 0.18-µm CMOS technology process and 1.8V power supply.