Jayadev Pavuluri, Sanjeev M. Ranjan, Alok Naugarhiya
{"title":"Analysis of Gate Oxides in LDMOS for Radiation Hardening Against SEGR","authors":"Jayadev Pavuluri, Sanjeev M. Ranjan, Alok Naugarhiya","doi":"10.1109/ICICCSP53532.2022.9862521","DOIUrl":null,"url":null,"abstract":"A brief analysis of Silicon on Insulator (SOI) LDMOS with various High-K Gate dielectrics under radiation environment was done in this paper. Four High-K gate dielectric stacks, $\\mathbf{Si}_{\\boldsymbol{3}}\\mathbf{N}_{\\boldsymbol{4}}-\\mathbf{SiO}_{\\boldsymbol{2}},\\mathbf{Al}_{\\boldsymbol{2}}\\mathbf{O}_{\\boldsymbol{3}}-\\mathbf{SiO}_{\\boldsymbol{2}}, \\mathbf{AlN}-\\mathbf{SiO}_{\\boldsymbol{2}},$ and $\\mathbf{HfO}_{\\boldsymbol{2}}-\\mathbf{SiO}_{\\boldsymbol{2}},$ are used to study the corresponding Strike fields, Breakdown voltages, and other significant parameters, and a comparison was made against Conventional LDMOS structure. It has been observed that the SOI LDMOS with $\\mathbf{HfO}_{\\boldsymbol{2}}-\\mathbf{SiO}_{\\boldsymbol{2}}$ gate dielectric and SOI LDMOS with $\\mathbf{Si}_{\\mathbf{3}}\\mathbf{N}_{\\mathbf{4}}-\\mathbf{SiO}_{\\mathbf{2}}$ gate dielectric provides better radiation hardening against SEGR compared to other dielectrics and SOI LDMOS with $\\mathbf{AlN}-\\mathbf{SiO}_{\\boldsymbol{2}}$ stack provides least radiation hardening against SEGR. The buried oxide layer modulates the electric field at the drift region and increases the Breakdown voltage. For an ion strike of linear energy transfer (LET) of 89 $\\mathbf{MeV.}\\mathbf{cm}^{\\boldsymbol{2}}/\\mathbf{mg}$, Strike fields of SOI LDMOS with $\\mathbf{RfO}_{\\boldsymbol{2}}-\\mathbf{SiO}_{\\boldsymbol{2}}$ gate dielectric and SOI LDMOS with $\\mathbf{Si}_{\\boldsymbol{3}}\\mathbf{N}_{\\boldsymbol{4}}-\\mathbf{SiO}_{\\boldsymbol{2}}$ gate dielectric are reduced by 15.3%, 28.8%, respectively compared to conventional LDMOS. For SOI LDMOS with $\\mathbf{RfO}_{\\boldsymbol{2}}-\\mathbf{SiO}_{\\boldsymbol{2}}$ gate dielectric, Breakdown voltage (BV) is increased by 20.09% compared to conventional LDMOS, and for SOI LDMOS with $\\mathbf{Si}_{\\boldsymbol{3}}\\mathbf{N}_{\\boldsymbol{4}}-\\mathbf{SiO}_{\\boldsymbol{2}}$ gate dielectric, BV is increased by 18.95%, compared to conventional LDMOS. Therefore, the Figure of Merit (FOM) of SOI LDMOS with $\\mathbf{HfO}_{\\boldsymbol{2}}-\\mathbf{SiO}_{\\boldsymbol{2}}$ gate dielectric and SOI LDMOS with $\\mathbf{Si}_{\\boldsymbol{3}}\\mathbf{N}_{\\boldsymbol{4}}-\\mathbf{SiO}_{\\boldsymbol{2}}$ gate dielectric is improved by 29.21 % and 40.9%, respectively. Proposed LDMOS structures can be used for designing DC-to-DC converters in the radiation environment, in aerospace and satellite applications.","PeriodicalId":326163,"journal":{"name":"2022 International Conference on Intelligent Controller and Computing for Smart Power (ICICCSP)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Intelligent Controller and Computing for Smart Power (ICICCSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICCSP53532.2022.9862521","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A brief analysis of Silicon on Insulator (SOI) LDMOS with various High-K Gate dielectrics under radiation environment was done in this paper. Four High-K gate dielectric stacks, $\mathbf{Si}_{\boldsymbol{3}}\mathbf{N}_{\boldsymbol{4}}-\mathbf{SiO}_{\boldsymbol{2}},\mathbf{Al}_{\boldsymbol{2}}\mathbf{O}_{\boldsymbol{3}}-\mathbf{SiO}_{\boldsymbol{2}}, \mathbf{AlN}-\mathbf{SiO}_{\boldsymbol{2}},$ and $\mathbf{HfO}_{\boldsymbol{2}}-\mathbf{SiO}_{\boldsymbol{2}},$ are used to study the corresponding Strike fields, Breakdown voltages, and other significant parameters, and a comparison was made against Conventional LDMOS structure. It has been observed that the SOI LDMOS with $\mathbf{HfO}_{\boldsymbol{2}}-\mathbf{SiO}_{\boldsymbol{2}}$ gate dielectric and SOI LDMOS with $\mathbf{Si}_{\mathbf{3}}\mathbf{N}_{\mathbf{4}}-\mathbf{SiO}_{\mathbf{2}}$ gate dielectric provides better radiation hardening against SEGR compared to other dielectrics and SOI LDMOS with $\mathbf{AlN}-\mathbf{SiO}_{\boldsymbol{2}}$ stack provides least radiation hardening against SEGR. The buried oxide layer modulates the electric field at the drift region and increases the Breakdown voltage. For an ion strike of linear energy transfer (LET) of 89 $\mathbf{MeV.}\mathbf{cm}^{\boldsymbol{2}}/\mathbf{mg}$, Strike fields of SOI LDMOS with $\mathbf{RfO}_{\boldsymbol{2}}-\mathbf{SiO}_{\boldsymbol{2}}$ gate dielectric and SOI LDMOS with $\mathbf{Si}_{\boldsymbol{3}}\mathbf{N}_{\boldsymbol{4}}-\mathbf{SiO}_{\boldsymbol{2}}$ gate dielectric are reduced by 15.3%, 28.8%, respectively compared to conventional LDMOS. For SOI LDMOS with $\mathbf{RfO}_{\boldsymbol{2}}-\mathbf{SiO}_{\boldsymbol{2}}$ gate dielectric, Breakdown voltage (BV) is increased by 20.09% compared to conventional LDMOS, and for SOI LDMOS with $\mathbf{Si}_{\boldsymbol{3}}\mathbf{N}_{\boldsymbol{4}}-\mathbf{SiO}_{\boldsymbol{2}}$ gate dielectric, BV is increased by 18.95%, compared to conventional LDMOS. Therefore, the Figure of Merit (FOM) of SOI LDMOS with $\mathbf{HfO}_{\boldsymbol{2}}-\mathbf{SiO}_{\boldsymbol{2}}$ gate dielectric and SOI LDMOS with $\mathbf{Si}_{\boldsymbol{3}}\mathbf{N}_{\boldsymbol{4}}-\mathbf{SiO}_{\boldsymbol{2}}$ gate dielectric is improved by 29.21 % and 40.9%, respectively. Proposed LDMOS structures can be used for designing DC-to-DC converters in the radiation environment, in aerospace and satellite applications.