Comparison of Various Adders and their VLSI Implementation

Abstract

It is profoundly accepted that the main processing unit of any device capable of carrying out computations is the Central Processing Unit (CPU) and the one of the most fundamental and integral part of CPU is an Arithmetic and Logical Unit (ALU) and adders are the primary and indispensable component of Arithmetic Logic Unit (ALU). The ALU is primarily responsible for carrying out the logical operation, arithmetic operations etc. Adders are also very important for Digital Signal Processing (DSP) for filter designing. Nowadays it has become very important to speed up all devices and make them more power efficient for lack of storage of huge amount of power and small in size for mobility. As adders are the main part of all these, it is of prime importance that we modify the adder in order to fetch maximum efficiency regarding - Propagation delay, Area on Chip and Power Consumption. Various adders have been invented so far which specializes in various work platform and they are efficient in their ways. This paper consists a comparative study on various parallel adders and proposes a hybrid adder. All the results of the Adders are carried out in Xilinx 14.7 ISE environment and coded using Verilog HDL. Specific graph and table of the values are given for propagation delay, area, number of transistors required for a better comparison.