Power Efficient Approach and Performance Control for Routers

Abstract

We introduce two approaches for power saving routers, which are the power efficient designing and the power saving designing. Power efficient designing enables a high performance router at low power consumption. As a part of power efficient designing, we have integrated ASICs/FPGAs of routers and developed a scalable central architecture. Additionally, we used new high speed memories and high speed interfaces such as a SerDes. As a result, the whole power consumption of our router adopting power efficient designing was reduced over 50% compared to conventional routers. Power saving designing is an approach to cut down wasted power consumption. Two major aspects belong to power saving designing, which are static performance control and dynamic performance control. We have been studying on static performance control, such as power cutting technology per port or module, and power saving mode by frequency switching. We were successful in saving 10-20% of power compared to conventional routers using this power saving mode by frequency switching. Furthermore, we introduce the dynamic performance control as a promising power saving approach for next generation routers. The router controls its performance dynamically according to the amount of received traffic. We show two technologies needed for this approach, which are the dynamically performance controllable router architecture/circuit, and the traffic monitoring/predicting technology. We consider that working on these technologies will save more power.