Introduction to the special section on ESTIMedia'10

Abstract

Embedded multimedia systems are one of the most representative segments of today’s electronics markets. However, their design complexity is increasing every year due to the convergence of a range of technologies as well as rapidly exploding user demands. Furthermore, their time-to-market is becoming more challenging. For holistic systemwide optimization, hardware and software are tightly coupled and separation between hardware and software design is no longer feasible. This special section presents the state-of-the-art results for designing embedded multimedia systems. The eighth edition of the IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) featured 14 high-quality technical papers, which were carefully selected from 27 submissions from all over the world. This special section features five articles, three of which were extended from ESTIMedia 2010. The range of the featured articles provides a glimpse of the current state-of-the-art in embedded systems for real-time multimedia. They cover a variety of topics including design-space exploration for MPSoC, automated generation of process networks, on-chip interconnects, scheduling of data flow, and fault resilience design for embedded multimedia applications. The article entitled A System-Level Infrastructure for Multidimensional MPSoC Design Space Co-Exploration by Z. J. Jia et al. presents a flexible and extensible systemlevel MP-SoC design space exploration (DSE) infrastructure. The article Automated Generation of Polyhedral Process Networks from Affine Nested-Loop Programs with Dynamic Loop Bounds by D. Nadezhkin et al. presents a first approach for automated translation of affine nested-loop programs with dynamic loop bounds into input-output equivalent Polyhedral Process Networks. Moreover, the method for calculating the first-in-first-out (FIFO) buffer sizes in such networks is also provided. The article entitled An Analytical Model for On-Chip Interconnects in Multimedia Embedded Systems by Y. Wu et al. presents a new analytical model to investigate the performance of the fat-tree based on-chip interconnection networks under bursty multimedia traffic and nonuniform message destinations. The article Scheduling of Synchronous Data Flow Models onto Scratchpad Memory-Based Embedded Processors by W. Che and K. S. Chatha presents a heuristic algorithm for scheduling synchronous data flow models on scratch pad memory-enhanced processors to minimize the steady-state execution time. The article Improving the Fault Resilience of an H.264 Decoder using Static Analysis Methods by F. Schmoll et al. presents a fault-tolerance approach for a H.264 decoder to select correction methods appropriate to error impact and current timing conditions. For this special section, at least three reviewers who are experts in their area provided numerous comments to the authors. We would like to thank all the authors who submitted manuscripts for this special section. Special thanks go to all the reviewers for their high standards so that we are able to present the high-quality articles in this