Fast Placement-Intact Logic Perturbation Targeting for FPGA Performance Improvement

C.L. Zhou, W. Tang, Yu-Liang Wu
{"title":"Fast Placement-Intact Logic Perturbation Targeting for FPGA Performance Improvement","authors":"C.L. Zhou, W. Tang, Yu-Liang Wu","doi":"10.1109/SPL.2007.371725","DOIUrl":null,"url":null,"abstract":"This work presents a novel, accurate, and fast post-layout logic perturbation method for improving LUT-based FPGA routing without affecting the placement. The ATPG-based rewiring techniques are used to design the rewiring engine, which is embedded into VPR, the most powerful academic FPGA CAD tool currently. Compared with VPR's high-quality results, our method can reduce critical path delay by up to 31.74% (avg. 10%) without disturbing placement or sacrificing area. The CPU time used by the rewiring engine is only 5% of the total time consumed by VPR's placement and routing. All the benchmark circuits can be placed and routed within 3 minutes, which is much faster than the SPFD approach. This paper also analyzes the power of the ATPG- based rewiring techniques in LUT-based FPGAs. Experimental results show that 3% of all nets can be replaced by their alternative wires for FPGA performance improvement.","PeriodicalId":419253,"journal":{"name":"2007 3rd Southern Conference on Programmable Logic","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 3rd Southern Conference on Programmable Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPL.2007.371725","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

This work presents a novel, accurate, and fast post-layout logic perturbation method for improving LUT-based FPGA routing without affecting the placement. The ATPG-based rewiring techniques are used to design the rewiring engine, which is embedded into VPR, the most powerful academic FPGA CAD tool currently. Compared with VPR's high-quality results, our method can reduce critical path delay by up to 31.74% (avg. 10%) without disturbing placement or sacrificing area. The CPU time used by the rewiring engine is only 5% of the total time consumed by VPR's placement and routing. All the benchmark circuits can be placed and routed within 3 minutes, which is much faster than the SPFD approach. This paper also analyzes the power of the ATPG- based rewiring techniques in LUT-based FPGAs. Experimental results show that 3% of all nets can be replaced by their alternative wires for FPGA performance improvement.
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快速放置-完整逻辑微扰瞄准FPGA性能改进
这项工作提出了一种新颖,准确,快速的布局后逻辑摄动方法,可以在不影响布局的情况下改善基于lut的FPGA路由。采用基于atpg的重布线技术设计了重布线引擎,并将其嵌入到目前最强大的FPGA CAD工具VPR中。与VPR的高质量结果相比,我们的方法可以在不干扰放置或牺牲面积的情况下将关键路径延迟减少31.74%(平均10%)。重新布线引擎使用的CPU时间仅为VPR放置和路由所消耗的总时间的5%。所有基准电路可以在3分钟内放置和路由,这比SPFD方法快得多。本文还分析了基于lut的fpga中基于ATPG的重布线技术的功率。实验结果表明,3%的网络可以被它们的备选线替代,从而提高FPGA的性能。
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