Design of high speed burst-mode BERT based on FPGA

Abstract

Being different from general continual-data stream BER tester, the receiver of burst-mode BER tester is required to extract clock and recover data accurately from the incoming datasteam characterized by phase variation within a dozen bits time before error bits detection is conducted, moreover, while error bits detecting, the receiver should filter the preamble and delimiter and execute error bits statistic only for Payload. In this paper a design method for Burst-mode BER Tester Based on FPGA is put forward. First of all, the whole structure of this design is introduced, and then the logic function modules implemented in the FPGA and system control program are presented in detail separately. The experimental results of applying this test equipment to 1.25G burst-mode optical receiver in GPON system illustrate that it has good performance and practical value.