A High-Gain, Low-Power Latch Comparator Design for Oversampled ADCs

Abstract

In this paper, the challenge of enhancing the gain and reducing the power requirements of latch comparators, preferably used in oversampled ADC is addressed. It is demonstrated that by designing the pre-amplifier stage using composite cascode differential structure, in which some transistors operate in subthreshold/ weak inversion region, high-gain (79 dB) at low-power (412nW) and low input noise (111.4nV/sqrt(Hz)) with 1.5V power supply, can be obtained through this stage. The succeeding latch circuitry is designed to enhance the comparator speed and to kickback noise effect. The proposed latch comparator operates at a low power consumption of 32μW and has a propagation delay of 0.78 ns only. The op-amp is designed using 180nm CMOS technology and simulations that demonstrate results are given.