High throughput Cholesky decomposition based on FPGA

Abstract

Cholesky decomposition has wide applications in solving many engineering and scientific problems. Acceleration is an important issue in many of these problems. In this paper, a hardware-based LLT Cholesky decomposition featuring high throughput has been presented to solve wiener filtering based on the minimum square error criterion. To achieve the best efficiency, the hardware-based implementation has been realized by fixed-point multiple structures and various pipeline stages. Parallel properties have been exploited to improve the throughput. Results have shown that a significant speedup has been achieved compared to the software-based approach.