{"title":"Efficient on-chip vector processing for multicore processors","authors":"S. F. Beldianu, Sotirios G. Ziavras","doi":"10.1109/ISSoC.2013.6675260","DOIUrl":null,"url":null,"abstract":"Per-core vector support in multicores is not efficient since applications rarely sustain high DLP. We present two Power Gating (PG) schemes to dynamically control Vector co-Processors (VPs) shared by cores. ASIC and FPGA modeling show that PG can reduce the energy by 33% while maintaining high performance.","PeriodicalId":228272,"journal":{"name":"2013 International Symposium on System on Chip (SoC)","volume":"23 9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 International Symposium on System on Chip (SoC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSoC.2013.6675260","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Per-core vector support in multicores is not efficient since applications rarely sustain high DLP. We present two Power Gating (PG) schemes to dynamically control Vector co-Processors (VPs) shared by cores. ASIC and FPGA modeling show that PG can reduce the energy by 33% while maintaining high performance.
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