Quantitative Comparison of Switching Strategies for Networks on Chip

Abstract

To ensure low power consumption while maintaining flexibility and performance, future systems-on-chip (SoC) will integrate many processor nodes and memory units. To interconnect these IP nodes, networks-on-chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. One major problem consists in being able to compare choices and strategies in NoC design. To tackle this problem, we propose a complete highly configurable framework called Polymorpher which enables a quantitative comparison of the performance and energy consumption of different NoC communication component architectures. Our models are based on a set of basic VHDL communication components that can be reused for different designs. This common test-bed allows us to fairly and accurately compare different types of communication components in terms of energy consumption, delay and area. In particular, the framework enables easy instantiation and exploration of different types of routers. We have chosen to explore different switching strategies and parameters as an example of the possibilities offered by our tool. Our study compares quantitatively different switching techniques widely used in NoCs (store and forward, virtual cut through, wormhole) in terms of power consumption, area overhead and delay with a post lay-out gate-level simulation.