Estimation of maximum currents for fault tolerant design of power distribution systems in integrated circuits

Abstract

Current flow in power distribution systems inside an integrated circuit (IC), especially in VLSI and wafer-scale ICs, causes problems of voltage drop and metal migration, leading to logic malfunction, reduction in operating speed, and reduction in the expected life span of a chip. Accurate estimations of currents are needed to design the power distribution systems so that they will withstand the adverse effects of current surges. During fabrication or as a result of aging, the power distribution systems may break at some weak points. As a result, some parts of the systems may have to route excessive amounts of currents. A power distribution system should be designed so that, in the presence of a limited number of these breaks, the system will deliver currents to the macro cells without violating some prescribed limits on voltage drops and without causing metal migration. The author deals with estimating currents in the segments of power distribution systems under fault conditions and develops guidelines for designing the systems so that the voltage drop and metal migration constraints with respect to these current estimates will not be violated.<>