Yoshihiro Watanabe, T. Komuro, S. Kagami, M. Ishikawa
{"title":"Parallel extraction architecture for image moments of numerous objects","authors":"Yoshihiro Watanabe, T. Komuro, S. Kagami, M. Ishikawa","doi":"10.1109/CAMP.2005.38","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a new architecture that can extract information of numerous objects in an image at highspeed. Various characteristics can be obtained from the image moments. The proposed architecture simultaneously extracts the moments of multiple objects in parallel. This parallel extraction enables a significant reduction in the amount of calculation required. In addition, asynchronous operation allows fast processing. We believe that our architecture can obtain more information in real-time even at high frame rates, providing advantages in a wide range of applications, mainly for image measurement. This paper describes our proposed architecture and some results on its implementation in FPGA.","PeriodicalId":393875,"journal":{"name":"Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAMP.2005.38","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper, we propose a new architecture that can extract information of numerous objects in an image at highspeed. Various characteristics can be obtained from the image moments. The proposed architecture simultaneously extracts the moments of multiple objects in parallel. This parallel extraction enables a significant reduction in the amount of calculation required. In addition, asynchronous operation allows fast processing. We believe that our architecture can obtain more information in real-time even at high frame rates, providing advantages in a wide range of applications, mainly for image measurement. This paper describes our proposed architecture and some results on its implementation in FPGA.