Design of a 1.8V/3.3V 100Mbps GPIO Transmitter for Intel Max 10 FPGA

Abstract

This paper presents the design of 1.8V/3.3V 100 Mbps General Purpose Input/Output (GPIO) transmitter for an Intel Max 10 FPGA. This transmitter works for both 1.8V and 3.3V IO supplies. The building blocks of this transmitter are level shifter and driver circuits. The level shifter is designed to level up the data levels from 0.8V to 1.8V/3.3V. A progressive sized driver circuit is designed to drive 50$\Omega$ termination resistance and the load capacitance of 5pF as per the requirement of Intel Max10. The overall design is carried out with 22nm technology node on cadence virtuoso platform and is simulated across PVT. The simulation results shows that the proposed design supports up to a data rate of 100Mbps with a power consumption of 1.59mW at 1.8V supply and with a power consumption of 2.93mW at 3.3V supply.