A New System Interconnection Architecture Based on RapidIO Using Partial Reconfiguration

Abstract

Now in the field of embedded system, high-speed interconnection based on parallel or serial LVDS technology is becoming increasingly important. Because of this the first RapidIO offerings available in the market were FPGA based, RapidIO interconnection had been identified as significant emerging technologies for FPGAs to support. At the same time, as the FPGAs increase in size, they are being large enough to accommodate both the static RapidIO interface and the reconfigurable logic. So, a consistent I/O interface is provided to support Reconfigurable Partition. This paper presents a new system interconnection architecture based on RapidIO to achieve the FPGA run-time Reconfigurable Partition.