Silicon Compilation-A Hierarchical Use of PLAs

Abstract

This paper proposes a way to compile a silicon layout directly from synchronous logic specification. The motivation for introducing compilation into the silicon world comes from its extreme success in the software world. As we see silicon area increasing and circuit complexity increasing, we might feel much in common with the early day programmers who faced increasing memory availability along with increasing program complexity. Software and hardware revolve around the same basic concern: The software designer lays out a one dimensional array of memory whereas the integrated circuit designer lays out a two dimensional area of silicon. In each case, various constraints must be satisfied in order to obtain a working product. In addition, both efforts involve lots of modification.