Yan Zhang, Shuqin Geng, Xiaohong Peng, Zifeng Wang, Haonan Tang, Shuaiqi Yan
{"title":"Research on Automatic Generation of Stimulator Based on CAN-FD Verification Platform","authors":"Yan Zhang, Shuqin Geng, Xiaohong Peng, Zifeng Wang, Haonan Tang, Shuaiqi Yan","doi":"10.1109/ICICM50929.2020.9292254","DOIUrl":null,"url":null,"abstract":"In this paper, we use Python script to read the function detailed description documents of CAN-FD IP, extract the required information according to the main keywords and other information, and automatically generate the qualified System Verilog constrained randomized register configuration stimulator. The simulation results show that the stimulator can meet the design requirements for the configuration of excitation, and can effectively improve the design efficiency of the verification platform.","PeriodicalId":364285,"journal":{"name":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM50929.2020.9292254","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, we use Python script to read the function detailed description documents of CAN-FD IP, extract the required information according to the main keywords and other information, and automatically generate the qualified System Verilog constrained randomized register configuration stimulator. The simulation results show that the stimulator can meet the design requirements for the configuration of excitation, and can effectively improve the design efficiency of the verification platform.