Finding an Efficient FPGA Implementation of the DES Algorithm to Support the Processor Chip on Smartcard

Abstract

The data security or information of any kind is essential to maintain its confidentiality. For that reason, we need a system that can maintain the security of such information. DES (Data Encryption Standard) becomes one of the algorithms that can be used in data and information security system. In this paper, we propose to get the best DES algorithm to apply on System on Chip (SoC). The analysis was performed by comparing between the 16-round pipelines DES algorithms which is the general DES algorithm with the 8-round pipeline DES algorithm which is the result of efficiency. The analysis was done with VHDL (Verilog High Definition Language) design language model and synthesized using XC3ES500E Field Programmable Gate Array (FPGA). The result of the average analysis of the overall resources required by each of the DES algorithms compared is that the 16-round DES requires an average of 21.2% of the resources, while the 8-round DES requires an average of only 9.7%. This shows that the 8-round DES pipeline algorithm is the best and efficient DES algorithm to apply on SoC as a data and information security system.