{"title":"A 6fJ/step, 5.5ps time-to-digital converter for a digital PLL in 40nm digital LP CMOS","authors":"J. Borremans, K. Vengattarmane, J. Craninckx","doi":"10.1109/RFIC.2010.5477312","DOIUrl":null,"url":null,"abstract":"A compact (0.01mm2) coarse-fine time-to-digital converter (TDC) in 40nm LP CMOS achieves 5.5ps resolution using parallel delay lines. A 6fJ/conversion step efficiency is achieved thanks to efficient residue calculation. A 0.8LSB single-shot precision and low DNL are reached thanks to simple calibration which is possible in fractional-N PLLs. Further, metastability avoidance and digital error correction are implemented. This 14-bit architecture operates at a 40MS/s reference clock.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2010.5477312","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A compact (0.01mm2) coarse-fine time-to-digital converter (TDC) in 40nm LP CMOS achieves 5.5ps resolution using parallel delay lines. A 6fJ/conversion step efficiency is achieved thanks to efficient residue calculation. A 0.8LSB single-shot precision and low DNL are reached thanks to simple calibration which is possible in fractional-N PLLs. Further, metastability avoidance and digital error correction are implemented. This 14-bit architecture operates at a 40MS/s reference clock.
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