{"title":"A 6GHz direct digital synthesizer MMIC with nonlinear DAC and wave correction ROM","authors":"Danyu Wu, Gaopeng Chen, Jianwu Chen, Xinyu Liu, Li-Xin Zhao, Zhi Jin","doi":"10.1109/RFIC.2010.5477279","DOIUrl":null,"url":null,"abstract":"This paper proposes a new DDS architecture combined with Nonlinear DAC and Wave-Correction-ROM (WCR) which shows both high operating speed and accuracy. Based on this architecture, a 6GHz 8-bit DDS MMIC is designed and fabricated in 60GHz GaAs HBT Technology. The DDS MMIC includes 8-bit pipeline accumulator, an 8×8×3bits WCR, two combined DACs and an analog Gilbert Cell for sine-wave generation with 8-bit amplitude resolution. The DDS chip is tested in on-wafer measurement system. The measured spurious free dynamic range (SFDR) is 33.96dBc with 2.367GHz output under a 6GHz maximum clock (FCW=0×65). It shows an average SFDR of 37.5dBc and the worst case SFDR of 31.4dBc (FCW=0×70) within the whole Nyquist band under a 5GHz clock frequency. The whole chip occupies 2.4×2mm2 of area consuming 3.27W of power from a single −4.6Vpower supply.","PeriodicalId":269027,"journal":{"name":"2010 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2010.5477279","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
This paper proposes a new DDS architecture combined with Nonlinear DAC and Wave-Correction-ROM (WCR) which shows both high operating speed and accuracy. Based on this architecture, a 6GHz 8-bit DDS MMIC is designed and fabricated in 60GHz GaAs HBT Technology. The DDS MMIC includes 8-bit pipeline accumulator, an 8×8×3bits WCR, two combined DACs and an analog Gilbert Cell for sine-wave generation with 8-bit amplitude resolution. The DDS chip is tested in on-wafer measurement system. The measured spurious free dynamic range (SFDR) is 33.96dBc with 2.367GHz output under a 6GHz maximum clock (FCW=0×65). It shows an average SFDR of 37.5dBc and the worst case SFDR of 31.4dBc (FCW=0×70) within the whole Nyquist band under a 5GHz clock frequency. The whole chip occupies 2.4×2mm2 of area consuming 3.27W of power from a single −4.6Vpower supply.
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