{"title":"Applying pipelining techniques to microprocessors","authors":"J. Slager, G. Louie, L. Gindraux, B. Rash","doi":"10.1145/1096458.1096460","DOIUrl":null,"url":null,"abstract":"Pipelining techniques are used in the Intel iAPX 286. High performance with full protection using normal speed memories require pipelining techniques. Pipelining gets the most done in each processor clock cycle. The internal pipelining is then exported to the memory bus to allow usage of slow memory devices.","PeriodicalId":138968,"journal":{"name":"ACM Sigmicro Newsletter","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1984-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM Sigmicro Newsletter","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1096458.1096460","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Pipelining techniques are used in the Intel iAPX 286. High performance with full protection using normal speed memories require pipelining techniques. Pipelining gets the most done in each processor clock cycle. The internal pipelining is then exported to the memory bus to allow usage of slow memory devices.