{"title":"Transmission Gate-Based 8T SRAM Cell for Biomedical Applications","authors":"Valluri Aswini, Sarada Musala, Avireni Srinivasulu","doi":"10.1109/ATEE52255.2021.9425314","DOIUrl":null,"url":null,"abstract":"There is an immense necessity of several kB of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate based SRAM cell for Biomedical applications eliminating the use of peripheral circuitry during the read operation. This topology offers smaller area, reduced delay, low power consumption and improved data stability in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45 V.","PeriodicalId":359645,"journal":{"name":"2021 12th International Symposium on Advanced Topics in Electrical Engineering (ATEE)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 12th International Symposium on Advanced Topics in Electrical Engineering (ATEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATEE52255.2021.9425314","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
There is an immense necessity of several kB of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate based SRAM cell for Biomedical applications eliminating the use of peripheral circuitry during the read operation. This topology offers smaller area, reduced delay, low power consumption and improved data stability in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45 V.