Michael C. Huang, Jose Renau, Seung-Moon Yoo, J. Torrellas
{"title":"Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips","authors":"Michael C. Huang, Jose Renau, Seung-Moon Yoo, J. Torrellas","doi":"10.1007/3-540-44570-6_11","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":226779,"journal":{"name":"Intelligent Memory Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Intelligent Memory Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/3-540-44570-6_11","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}