Low-power carry-select adder using adaptive supply voltage based on input vector patterns

Abstract

Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose adaptive supply voltage carry-select adder (CSA) based on the input vector patterns. A proposed level converter based on the complementary pass transistor logic (CPL) cancels out the delay penalty of level conversion. We achieved 26% power improvement on a 128-bit CSA prototype over a conventional design with same performance.