Use of Symmetric Multiprocessor Architecture to achieve high performance computing

Abstract

In this paper, the objective is to investigate different performance enhancement attributes in multiprocessors architectures. We investigate the problem of cache hit and cache miss by efficient cache partitioning technique. We improved power efficiency by handling cache misses during data transfer from main memory to cache. The focus is on cache utilization techniques, cache partitioning techniques, power utilization by different components, parallel processing issues and limitation in multiple processors. We evaluate the parameters which use the cache and processors to achieve highest level performance. In this way the workload between different processes can be handled easily.