Asymmetrical Multilevel Inverter Topology

Anilkumar Chappa, Gowthami Seethala, Sudha Rani Donpeudi, C. Rambabu
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Abstract

Multilevel inverters (MLIs) are being extensively used in high voltage/power applications due to their superior features like lesser dv/dt stress on switches and less harmonic distortion over two level inverters. However for higher number of levels, there is a considerable increase of number of power switches, voltage stress and dc voltage sources. The increased device count directly affects the cost of the inverter and also makes the system complex. In order to improve the output voltage levels, an MLI topology is proposed in this paper with less device count. The proposed topology can generate 7-level and 11-level output voltage in asymmetric source configuration with a single cell, by using multi carrier pulse width modulation (MC-PWM) technique. Further, the superior characteristics of the proposed topology have been proved by comparing with the recent literature. The robustness and vulnerability of the proposed topology has been verified through simulation analysis under different operating conditions.
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非对称多电平逆变器拓扑
多电平逆变器(mli)由于其优越的特性,如开关上的dv/dt应力较小,以及两电平逆变器上的谐波失真较小,因此被广泛用于高压/功率应用。然而,对于更高的电平数,功率开关、电压应力和直流电压源的数量会有相当大的增加。器件数量的增加直接影响逆变器的成本,也使系统变得复杂。为了提高输出电压水平,本文提出了一种器件数量较少的MLI拓扑结构。该拓扑通过多载波脉宽调制(MC-PWM)技术,可以在单单元非对称源配置下产生7电平和11电平输出电压。此外,通过与最近的文献比较,证明了所提出的拓扑结构的优越特性。通过仿真分析,验证了该拓扑在不同工况下的鲁棒性和脆弱性。
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