{"title":"Low power mixed analog-digital signal processing","authors":"Mattias Duppils, C. Svensson","doi":"10.1145/344166.344201","DOIUrl":null,"url":null,"abstract":"The power consumption of mixed-signal systems featured by an analog front-end, a digital back-end, and with signal processing tasks that can be computed with multiplications and accumulations, is analyzed. An implementation is proposed, composed of switched-capacitor mixed analog/digital multiply-accumulate units in the analog front-end, followed by an A/D converter. This implementation is shown to be superior in respect of power consumption compared to an equivalent implementation with a high-speed A/D converter in the front-end, to execute signal processing tasks that include decimation. The power savings are only due to relaxed requirement on A/D conversion rate, as a direct consequence of the decimation. In a case study of a narrowband FIR filter, realized with four multiply-accumulate units, and with a decimation factor of 100; power saving is 54 times. Implementation details are given, the power consumption, and the thermal noise are analyzed.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/344166.344201","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The power consumption of mixed-signal systems featured by an analog front-end, a digital back-end, and with signal processing tasks that can be computed with multiplications and accumulations, is analyzed. An implementation is proposed, composed of switched-capacitor mixed analog/digital multiply-accumulate units in the analog front-end, followed by an A/D converter. This implementation is shown to be superior in respect of power consumption compared to an equivalent implementation with a high-speed A/D converter in the front-end, to execute signal processing tasks that include decimation. The power savings are only due to relaxed requirement on A/D conversion rate, as a direct consequence of the decimation. In a case study of a narrowband FIR filter, realized with four multiply-accumulate units, and with a decimation factor of 100; power saving is 54 times. Implementation details are given, the power consumption, and the thermal noise are analyzed.