Evaluation of testability of digital circuits by fault injection technique

Abstract

Testing simple circuits or digital blocks can be actually done easily but testing a complex circuits before it is implemented is a challenge. To accomplish such testing, this paper presents a fault injection technique using package to inject transient and permanent fault at the VHDL level description of both combinational and sequential digital circuits to verify the testability of the circuits using online and offline testing. Injection of permanent fault and transient fault are done in the digital circuits such as 4 bit adder, 4 bit counter, two benchmark circuits C17 and S27 and their testabilities are evaluated. Fault coverage for permanent fault and transient fault is found to be 95% and 100% respectively.