Stochastic multiplier and divider for stochastic LU decomposition

Abstract

In this paper, designing of stochastic multiplier and divider is proposed for designing of Lower-Upper decomposition (LUD) scheme. By using stochastic computation complicated operations of LUD can be performed by simple logic gates. By using stochastic multiplier and divider computational complexity is reduced. Stochastic multiplier and divider use the stochastic stream which reduces the computational complexity by minimizing the stream length. The problems in Lower-Upper decomposition with stochastic stream are long computational latency and large computation variance. Dual partition based computation scheme which reduces input stream length is used to overcome the challenges. The design and implementation of stochastic LUD is carried out using Cadence Encounter tool. We have designed stochastic multiplier, divider and stochastic LUD with CMOS 180nm technology.