Parametric Hierarchy Recovery in Layout Extracted Netlists

Abstract

Modern IC design flows depend on hierarchy to manage the complexity of large-scale designs, however, due to the increased impact of long-range layout context on device behavior, extraction tools flatten these designs. As a result, in post-layout extraction, the hierarchy is lost and the designs are flattened, increasing both the size of the design database, and the amount of runtime that is needed to process these designs. In this paper, the idea of parametric hierarchy recovery is proposed that takes net lists extracted from the design layout, and recovers their hierarchical structure while preserving parametric accuracy. This decreases the size of the netlist and enables the use of hierarchical comparison methods and analysis. Our experiments show that in physical verification this method leads to a 70% reduction in runtime on average without any parametric error. Furthermore, this method can be used to provide tractable timing and power analysis that utilizes detailed transistor information in the presence of systematic layout-dependent variation.