C. Augustine, A. Afzal, U. Misgar, A. Owahid, A. Raman, K. Subramanian, F. Merchant, J. Tschanz, M. Khellah
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引用次数: 0
Abstract
A 10nm 4-core x86 IP with multiple low-power states including C1 (clock-gated core), C6 (power-gated core) and a new state called C1LP where the core voltage is lowered to its retention voltage (VRETENTION) is presented. All-digital closed-loop unified retention clamp for C1LP and wake up for C6 shows power savings of 33%/28% for core/IP, with 120ns wake up latency while addressing impact of PVT variations.
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