Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays

Yi Wang, W. Luk, Xuan Zeng, Jun Tao, Changhao Yan, J. Tong, W. Cai, Jia Ni
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引用次数: 11

Abstract

In nanometer technologies, process variations possess growing nonlinear impacts on circuit performance, which causes critical path delays of combinatorial circuits variate randomly with non-Gaussian distribution. In this paper, we propose a novel clock skew scheduling methodology that optimizes timing yield by handling non-Gaussian distributions of critical path delays. Firstly a general formulation of the optimization problem is proposed, which covers most of the previous formulations and indicates their limitations with statistical interpretations. Then a generalized minimum balancing algorithm is proposed for effectively solving the skew scheduling problem. Experimental results show that the proposed method significantly outperforms some representative methods previously proposed for yield optimization, and could obtain timing yield improvements up to 33.6% and averagely 17.7%.
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考虑非高斯分布关键路径延迟的时序良率驱动时钟偏差调度
在纳米技术中,工艺变化对电路性能的非线性影响越来越大,导致组合电路的关键路径延迟随机地呈非高斯分布。在本文中,我们提出了一种新的时钟偏差调度方法,该方法通过处理关键路径延迟的非高斯分布来优化时序产率。首先提出了优化问题的一般表述,它涵盖了以往的大多数表述,并用统计解释指出了它们的局限性。然后提出了一种广义最小平衡算法,有效地解决了倾斜调度问题。实验结果表明,所提方法明显优于已有的成品率优化方法,可获得最高达33.6%、平均17.7%的时序成品率改进。
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