C. Seguna, E. Gatt, I. Grech, O. Casha, G. Cataldo
{"title":"Development of an New ASIC based, Multi-channel Data Acquisition and Real-Time Processing System","authors":"C. Seguna, E. Gatt, I. Grech, O. Casha, G. Cataldo","doi":"10.1109/ICIT46573.2021.9453615","DOIUrl":null,"url":null,"abstract":"This work presents the development of a newly Application Specific Integrated Circuit suitable for the simultaneous readout, real-time measurement, and processing of digital data in a multi-channel data acquisition system. High-speed multi-channel digitizers are useful for large-scale high-energy physics, astrophysics, nuclear and plasma physics experiments. The developed application specific integrated circuit allows the simultaneous continuous readout and processing of 240 12-bit analogue channels, at data transfer rates of 4.0 Gbps via five 3-lane Low-Voltage Differential Signaling transmitter drivers. Additionally, unlike the various vendor-defined high-speed digitizers that are currently available in the market, the developed ceramic quad flat 160-pin package microelectronic circuitry includes the implementation of an integrated fault tolerant and recoverable Triple-Modular Redundancy voting circuitry, use of Zero-suppression compression algorithm and implementation of Cyclic-Redundancy Check technique. The integration of such features reduces development time and enables the developed integrated circuitry to be used in a radiation physics environment where single-event upset or latch-up could lead to event data corruption or even electronic failures. The implemented system architecture lowers maintenance costs, and further improves system performance by ten-fold when compared for example to other various data acquisition readout electronic systems currently present in the A Large Ion Collider experiment in CERN. Additionally, the developed XFAB 180 nm 6-layer parallel readout integrated circuit architecture can be easily interfaced with other various vendor-specific analogue-to-digital convertor modules that are currently available on the market, thus further facilitating the upgrading process of data acquisition systems.","PeriodicalId":193338,"journal":{"name":"2021 22nd IEEE International Conference on Industrial Technology (ICIT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 22nd IEEE International Conference on Industrial Technology (ICIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIT46573.2021.9453615","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This work presents the development of a newly Application Specific Integrated Circuit suitable for the simultaneous readout, real-time measurement, and processing of digital data in a multi-channel data acquisition system. High-speed multi-channel digitizers are useful for large-scale high-energy physics, astrophysics, nuclear and plasma physics experiments. The developed application specific integrated circuit allows the simultaneous continuous readout and processing of 240 12-bit analogue channels, at data transfer rates of 4.0 Gbps via five 3-lane Low-Voltage Differential Signaling transmitter drivers. Additionally, unlike the various vendor-defined high-speed digitizers that are currently available in the market, the developed ceramic quad flat 160-pin package microelectronic circuitry includes the implementation of an integrated fault tolerant and recoverable Triple-Modular Redundancy voting circuitry, use of Zero-suppression compression algorithm and implementation of Cyclic-Redundancy Check technique. The integration of such features reduces development time and enables the developed integrated circuitry to be used in a radiation physics environment where single-event upset or latch-up could lead to event data corruption or even electronic failures. The implemented system architecture lowers maintenance costs, and further improves system performance by ten-fold when compared for example to other various data acquisition readout electronic systems currently present in the A Large Ion Collider experiment in CERN. Additionally, the developed XFAB 180 nm 6-layer parallel readout integrated circuit architecture can be easily interfaced with other various vendor-specific analogue-to-digital convertor modules that are currently available on the market, thus further facilitating the upgrading process of data acquisition systems.