A heuristic for logical data buffer allocation in multicore platforms

Abstract

In the past memory allocation and communication between processors and memories in current MPSoC's, due to the small design space, was not a big challenge. Through advanced MPSoC's and improving techniques to interface Dynamic RAM (DRAM), allocation of logical data buffers to physical memories is no longer manageable manually. We present a heuristic for the mapping of logical data buffers to physical memories and the routing of data flows. Our heuristic use an approximation scheme to obtain an fractional solution, and randomized rounding. We evaluate our implementation for different values of e using representative data of the Long Term Evolution Standard.