Logic-based row redundancy technique designed in 7nm FinFET technology for embedded SRAMs

Abstract

In this paper, a row-redundancy circuit using latches is designed for 7nm FinFET ultra high density SRAM operating at 1.75 GHz. Input and faulty addresses are compared in parallel to the memory read access operation thus avoiding a major impact on access or address setup time. Latch output data is multiplexed with memory data and the impact on access time is only 7ps at SS/0.675V/-40°C corner. Data is written to redundant latches only when address comparison matches. The proposed circuit is implemented with no setup time impact and an overall area overhead of the proposed row redundancy scheme is less by 82% as compared to the area overhead of the conventional redundancy scheme.