Simplified path metric updating in the M algorithm for VLSI implementation

L. González, E. Boutillon
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引用次数: 3

Abstract

A VLSI structure for path metric updating in the M algorithm is presented. The architecture is based on the combination of a modified Batcher's (1968) odd-even merging network and a bitonic selection procedure. A feature of the trellis structure allows to replace an existing solution based on two 2M-item sorting operations by three M-item sorting operations with an additional one-layer bitonic merge. These three sorting networks and the bitonic merging procedure permit a reduction of up to 50% in hardware complexity.
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VLSI实现中M算法路径度量更新的简化
提出了一种用于M算法中路径度量更新的VLSI结构。该结构是基于改进的Batcher's(1968)奇偶合并网络和双音选择程序的结合。网格结构的一个特性允许将基于两个2m项目排序操作的现有解决方案替换为三个m项目排序操作,并附带一个额外的单层bitonic合并。这三种排序网络和bitonic合并过程允许将硬件复杂性降低多达50%。
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