Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs

H. Asadi, S. Miremadi, H. Zarandi, A. Ejlali
{"title":"Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs","authors":"H. Asadi, S. Miremadi, H. Zarandi, A. Ejlali","doi":"10.1109/PRDC.2004.1276583","DOIUrl":null,"url":null,"abstract":"The technology of SRAM-based devices is sensible to single event upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. We present a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used to experimentally evaluate the method. The results show that between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device.","PeriodicalId":383639,"journal":{"name":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PRDC.2004.1276583","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 19

Abstract

The technology of SRAM-based devices is sensible to single event upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. We present a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used to experimentally evaluate the method. The results show that between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于sram的fpga的容错设计评估
基于sram的器件技术对主要由高能重离子和中子引起的单事件扰动(seu)很敏感。我们提出了一个框架,用于评估使用模拟seu在基于sram的fpga上实现的容错设计。SEU注入过程是通过使用设备的配置位流文件将模拟的SEU插入设备中来完成的。使用Altera FPGA Flex10K200和ITC’99基准电路对该方法进行了实验评估。结果表明,注入器件的seu中有32%至45%传播到器件的输出端。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
The system recovery benchmark Availabilities and costs of reliable Fat-Btrees Application-level fault tolerance in the orbital thermal imaging spectrometer Expected-reliability analysis for wireless CORBA with imperfect components Failure handling in a reliable multicast protocol for improving buffer utilization and accommodating heterogeneous receivers
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1