{"title":"High-Energy Physics on DECPeRLe-1 Programmable Active Memory","authors":"L. Moll, J. Vuillemin, P. Boucard","doi":"10.1145/201310.201318","DOIUrl":null,"url":null,"abstract":"The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (RD-11) group and DECPRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third International ACM Symposium on Field-Programmable Gate Arrays","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/201310.201318","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
Abstract
The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (RD-11) group and DECPRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.