UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI

Abstract

In this paper, we propose an efficient approach to minimize total power (switching, short-circuit, and leakage power) without performance loss for ultra-low power CMOS circuits in nanometer technologies. We present a framework for combining supply/threshold voltage scaling, gate sizing, and interconnect scaling techniques for power optimization and propose an efficient heuristic algorithm which ensures that the total slack budget is maximal and the total power is minimal in the presence of back end (post-layout-based) UDSM effects. We have tested the proposed algorithms on a set of benchmark circuits and some building blocks of a synthesizable ARM core. The experimental results show that our polynomial-time solvable strategy delivers over an order of magnitude savings in total power without compromising performance.