An algorithm for reduced order modelling of digital controllers

A. Sahani, S. K. Nagar, J. Pal
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Abstract

An algorithm for designing reduced order digital controller which can replace an existing high order cascade digital controller is presented. The parameters of the reduced order controller are obtained by applying frequency response technique. The new algorithm is illustrated by some examples.
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数字控制器的降阶建模算法
提出了一种可替代现有高阶串级数字控制器的降阶数字控制器设计算法。应用频率响应技术得到了降阶控制器的参数。通过算例对新算法进行了说明。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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