Pulse Width Amplitude Modulation Based CMOS Multiplier

R. Astro, H. Gómez, Jhoan Salinas, A. Díaz-Sánchez
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引用次数: 1

Abstract

In this paper, a pulse width amplitude modulation multiplication scheme, that uses a novel flipped voltage follower (FVF) based current switch is presented. Simulations performed in Hspice with the standard AMI 0.5µm CMOS process shows a system with dynamic range of ±140 mV for both input signals with a maximum gain error of 1.1%. The circuit works with VDD = 3 V and a power consumption of 2.2 mW. The multiplier has a bandwidth of 16 kHz.
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基于脉宽调幅的CMOS乘法器
本文提出了一种脉宽调幅倍增方案,该方案采用一种新颖的基于翻转电压从动器的电流开关。在Hspice中使用标准AMI 0.5µm CMOS工艺进行了仿真,结果表明系统在两个输入信号的动态范围均为±140 mV,最大增益误差为1.1%。该电路工作在VDD = 3 V,功耗为2.2 mW。乘法器的带宽为16千赫。
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