{"title":"A fully differential, vertically structured and compensated subranging A/D-converter","authors":"P. Low","doi":"10.1109/IMTC.1994.351966","DOIUrl":null,"url":null,"abstract":"This paper introduces the design of a vertically structured subranging A/D-Converter. The vertically structured analog subranging circuits combined with the most common flash ADC led to the development of a converter for high conversion rates up to a resolution of 12 Bit. The compensation of the analog circuits reduces linearity errors to a minimum. Special attention has been paid on the differential architecture of the analog subranging circuits. The major advantage of this architecture is the improvement of the SNR and the reduction of errors caused by symmetrical parasitic impedances. New results are presented with a hybrid test circuit for a 10 Bit 30 Ms/s converter.<<ETX>>","PeriodicalId":231484,"journal":{"name":"Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMTC.1994.351966","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
This paper introduces the design of a vertically structured subranging A/D-Converter. The vertically structured analog subranging circuits combined with the most common flash ADC led to the development of a converter for high conversion rates up to a resolution of 12 Bit. The compensation of the analog circuits reduces linearity errors to a minimum. Special attention has been paid on the differential architecture of the analog subranging circuits. The major advantage of this architecture is the improvement of the SNR and the reduction of errors caused by symmetrical parasitic impedances. New results are presented with a hybrid test circuit for a 10 Bit 30 Ms/s converter.<>
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