Parallel memories in video encoding

Abstract

Summary form only given. A novel architecture with parallel memories suitable for hybrid video coding is presented. It efficiently relieves the memory bandwidth bottleneck in motion estimation, DCT, and IDCT involved in the real-time low-bit rate ITU-T H.263 video compression standard. There are four parallel processing elements and eight parallel memory blocks in the system. The address space is divided into three areas. Coordinate areas 0 and 1 can be accessed simultaneously for row or column formats, needed in the motion estimation, DCT, and IDCT. Alternatively, the area 2 can be accessed for a more complex formats. Such formats are needed, for example, in zigzag scanning and interpolation. The module assignment function S(i,j), expresses how data is stored in the memory modules. We can describe the memory space as a 2D coordinate system with horizontal and vertical coordinates (i,j). The coordinate values are restricted to positive values, and (0,0) is fixed to the uppermost left corner of the coordinate area. The function S(i,j) simply describes the memory block, where the value of coordinate point (i,j) is stored. Memory addresses are described by the address function a(i,j). The coordinate area 0 deals with the memory blocks 0...3, the area 1 with the blocks 4...7 and the area 2 with the blocks 0...7. The constants a/sub 0max/ and a/sub 1max/ are the maximum addresses of the coordinate areas 0 and 1, respectively. The width of the coordinate area is given by L/sub i/. The processing power increases linearly with the number of parallel processing elements. Using more parallel memory blocks enables use of more access formats.