Vedic Multiplier in 45nm Technology

Abstract

Multipliers in a digital processor remains as a core of mathematical computing paradigm. In ancient times Vedic mathematicians developed basic multiplication algorithms. This study focuses on optimizing area and designing the multiplier in 45 nanometer CMOS technology. Layout design and verification of a 4-bit multiplier is carried out. Operating voltage ranges from 0.9V to 1.1V, this aids in low power operation or the multiplier. Consuming 3.795uW of power in the highest constraint situation. "Layout Versus Schematic" and "Design Rule Check" (LVS & DRC) are the two software verification tools used to verify the integrated circuit design. Delay and power analysis of the multiplier using Cadence virtuoso manager are discussed. Delay of the proposed 4-bit multiplier in 45nm CMOS technology multiplier is 250ps by including all constraints.